Semiconductor device having laminated structure
US7875980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2005 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Aug 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.