Floating well circuit operable in a failsafe condition and a tolerant condition
US7876132B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Oct 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.