DLL circuit and semiconductor device having the same
US7876138B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2008 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.