Method for aligning a serial bit stream with a parallel output
US7876244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | May 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/041
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.