Memory cell array with specific placement of field stoppers
US7876610B2 · kind B2 · utility
6Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Nov 20, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.