Phase error de-glitching circuit and method of operating
US7876853B2 · kind B2 · utility
6Cited by
63References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2010 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Apr 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/99
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.