Concealment of external array accesses in a hardware simulation accelerator
US7877249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2006 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method detect external requests to access a memory array in a hardware simulation accelerator during performance of a simulation on a simulation model and access the memory array without halting the simulation in response to detecting the external request. Such functionality may be provided, for example, by detecting such external requests in response to processing a predetermined instruction in an instruction stream associated with the simulation model, where the predetermined instruction is configured to ensure a predetermined period of inactivity for the memory array. By doing so, the memory array can be accessed from outside of the hardware simulation accelerator during the processing of a simulation, and without requiring that the simulation be halted, thus reducing overhead and improving simulation efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.