Scalable distributed routing scheme for PCI express switches
US7877536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Nov 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.