Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region
US7879703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2009 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0179
Abstract
A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.