Patent · US Active

Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip

US7880261B2 · kind B2 · utility

0Cited by

2References

7Claims

0Family size

Assignee

NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

Peter J. Hopper · San Jose, US
William French · San Jose, US
Ann Gabrys · Woodside, US

Key dates

Filing date	Jul 1, 2008
Grant date	Feb 1, 2011
Priority date	—
Expiry date	Dec 21, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76264
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.