Periodic timing jitter reduction in oscillatory systems
US7880554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2009 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | May 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.