Semiconductor memory device
US7881120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2009 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jul 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.