Circuit providing load isolation and memory domain translation for memory module
US7881150B2 · kind B2 · utility
126Cited by
125References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.