Method and circuit for local clock generation and smartcard including it thereon
US7881894B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 10, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Mar 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.