Packet processing switch and methods of operation thereof
US7882280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jan 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.