Compute unit with an internal bit FIFO circuit
US7882284B2 · kind B2 · utility
5Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2007 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.