Managing cache memory in a parallel processing environment
US7882307B1 · kind B1 · utility
78Cited by
15References
39Claims
0Family size
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Key dates
| Filing date | Apr 14, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jan 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.