Monitor pattern of semiconductor device and method of manufacturing semiconductor device
US7883982B2 · kind B2 · utility
0Cited by
19References
4Claims
0Family size
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Key dates
| Filing date | Mar 5, 2009 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Mar 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.