Method of fabricating self aligned Schottky junctions for semiconductor devices
US7884002B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2006 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Oct 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.