Speed recognition for half bridge control
US7884583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Aug 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6871
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuit and method for controlling a high bridge circuit with increased efficiency is disclosed. Circuitry is provided outputting gating signals to a high side driver and a low side driver responsive to a time varying input signal. A frequency measurement circuit determines a high speed mode when the input signal is at a frequency above a threshold, and the gating signal to the high side driver is inhibited. When the input signal frequency is below the threshold, the low side driver and the high side driver gating signals switch alternately. In an exemplary implementation, the frequency measurement circuit is provided as two counters outputting signals to a decision circuit which controls the half bridge circuit. Methods are provided for efficiently providing gating signals to the drivers of a half bridge circuit based upon the frequency of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.