Techniques for adjusting level shifted signals
US7884644B1 · kind B1 · utility
7Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2010 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Feb 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.