Application delay analysis
US7885200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2006 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/75
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A graphic user interface facilitates the hierarchical analysis of timing parameters related to network-based applications. At the top level of the hierarchy, the user is presented a summary of the delays incurred while running an application, or while simulating the running of an application, organized by delay categories, including processing delays at each node, as well as propagation delays at each link between nodes. The interface enables a user to “drill down” into lower levels of the timing information hierarchy by ‘clicking’ on currently displayed information. The information is presented in a form most appropriate to the level of analysis. The presentation forms include, for example, pie-charts, multi-variable timing diagrams (in both absolute and relative forms), data exchange charts, and so on, and ‘zoom’ capabilities are provided as appropriate to the particular display form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.