Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations
US7886132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.