Visual yield analysis of intergrated circuit layouts
US7886238B1 · kind B1 · utility
7Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.