Patent · US Active

System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization

US7886262B2 · kind B2 · utility

15Cited by

1References

14Claims

0Family size

Inventors

Marko P. Chew · Cupertino, US
Yue Yang · Chengdu, CN

Key dates

Filing date	Aug 1, 2007
Grant date	Feb 8, 2011
Priority date	—
Expiry date	Dec 2, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.