Semiconductor device and method of manufacturing the same
US7888212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2009 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Feb 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.