Method of manufacturing an integrated circuit, an integrated circuit, and a memory module
US7888228B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jul 11, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a memory device includes, generating a solid electrolyte layer including a first solid electrolyte layer area and a second solid electrolyte layer area, the height of the top surface of the solid electrolyte layer within the second solid electrolyte layer area being lower than the height of the top surface of the solid electrolyte layer within the first solid electrolyte layer area; generating a conductive layer above the top surfaces of the first solid electrolyte layer area and the second solid electrolyte layer area; planarizing the top surface of the conductive layer such that the solid electrolyte layer is exposed within the first solid electrolyte layer area, however is covered by the conductive layer within the second solid electrolyte layer area; patterning the exposed solid electrolyte layer within the first solid electrolyte layer area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.