Electrical connections for multichip modules
US7888806B2 · kind B2 · utility
8Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jan 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. The first chip includes a plurality of metal lines which may be deposited at its top surface, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.