Hybrid delta-sigma ADC
US7889108B2 · kind B2 · utility
7Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2009 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | May 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.