Memory device and method of controlling read level
US7889563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2009 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Aug 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are memory devices and read level controlling methods. A memory device may include: a memory cell array that includes a plurality of memory cells; a counter that counts a number of memory cells with a threshold voltage included in a reference threshold voltage interval among the plurality of memory cells; a first decision unit that compares the counted number of memory cells with a threshold value to thereby decide whether to set a read level based on the reference threshold voltage interval; and a second decision unit that generates a new reference threshold voltage interval based on the comparison result between the counted number of memory cells and the threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.