Scalable VLSI architecture for K-best breadth-first decoding
US7889807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Oct 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03426
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.