Patent · US Active

Jitter estimation in phase-locked loops

US7890279B1 · kind B1 · utility

5Cited by

0References

17Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Daniel Tun Lai Chow · Foster City, US
San Wong · Cupertino, US
Vincent K. Tsui · Emeryville, US
Lik Huay Lim · Bukit Mertajam, MY
Man On Wong · Air Itam, MY

Key dates

Filing date	Aug 11, 2008
Grant date	Feb 15, 2011
Priority date	—
Expiry date	Mar 6, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/08
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.