Clock data recovery and synchronization in interconnected devices
US7890788B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 9, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Dec 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.