Method and apparatus of cache assisted error detection and correction in memory
US7890836B2 · kind B2 · utility
6Cited by
7References
7Claims
0Family size
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Key dates
| Filing date | Dec 14, 2006 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Dec 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.