Methods and apparatus for merging coverage for multiple verification and design scenarios
US7890902B1 · kind B1 · utility
5Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.