Integrated devices on a common compound semiconductor III-V wafer
US7893463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2010 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | May 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated pair of HBT and FET transistors shares a common compound semiconductor III-V epitaxial layer. The integrated pair of transistors includes a semi-insulating substrate of a compound semiconductor III-V material, a first epitaxial structure disposed on top of the substrate, a second epitaxial structure on top of the first epitaxial structure, and a third epitaxial structure disposed on top of the second epitaxial structure. The first epitaxial structure forms a portion of the HBT transistor. A concentration profile of a first contaminant, which contributes electrical charge, decreases substantially smoothly across an interface between the semi-insulating substrate and the first epitaxial structure. In some cases, the interface is free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.