Semiconductor device with charge storage pattern and method for fabricating the same
US7893484B2 · kind B2 · utility
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Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.