Power latch
US7893566B2 · kind B2 · utility
6Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2009 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jul 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.