Leakage compensation and improved setup/hold time in a dynamic flip-flop
US7893726B1 · kind B1 · utility
3Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.