Clock signal dividing circuit
US7893742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Feb 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.