Successive approximation register analog-digital converter and method of driving the same
US7893860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2009 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.