Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
US7894290B2 · kind B2 · utility
3Cited by
5References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Feb 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a system including a memory device. The method includes, upon receiving a request for an internal hidden refresh for the memory device, latching external command, address, and data information for the memory device. The method further includes placing the memory device in a standby state and during the standby state, performing the internal hidden refresh. The method further includes, after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.