Clock recovery circuit and a method of generating a recovered clock signal
US7894563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Apr 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a clock recovery circuit for generation of a recovered clock signal from a received data stream using a weighted combination of phase component signals. The clock recovery circuit comprises: a detector to detect the phase of a received data stream; a selector comprising a differential generator arranged to generate at least two related signals in dependence on the detected phase; and a clock signal generator to receive the at least two related signals and select related proportions of two or more of a plurality of phase component signals for combination, thereby to generate a recovered clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.