Hybrid cache coherence using fine-grained hardware message passing
US7895400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Dec 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.