Secure processor arrangement
US7895447B2 · kind B2 · utility
4Cited by
3References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2004 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | May 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.