Memory card with power saving
US7895457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Oct 4, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.