Bus failure management method and system
US7895493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Feb 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.