Error control coding methods for memories with subline accesses
US7895502B2 · kind B2 · utility
11Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, the whole codeword is read for error correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.