Method and apparatus for implementing a processor interface block with an electronic design automation tool
US7895549B1 · kind B1 · utility
6Cited by
0References
25Claims
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Assignee
Inventor
Key dates
| Filing date | Nov 23, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Apr 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.