Methods for forming silicide conductors using substrate masking
US7897500B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.